1. Field of the Invention
The present disclosure relates to a semiconductor device and a method of manufacturing the same and particularly to a semiconductor device and a method of manufacturing the same where the integrated circuit chip is bonded at its back side with a support member.
2. Description of the Related Art
Recently, as electronic appliances have been reduced in the overall dimensions, their mounted semiconductor devices are demanded to be increased in the mount concentration and minimized in the thickness and favorably marketed in the form of so-called surface mount type packages. For the surface mounting with LSI devices, a technique is known as ball grid array (BGA) where an array of spherical solder drops termed solder bumps which serve as external connector terminals are disposed two-dimensionally on one side of the package. Another technique of chip size package (CSP) is known where the package carrying a BGA arrangement is minimized to a size substantially equal to the size of a semiconductor chip for implementing the structure at extremely higher density and smaller thickness.
Some of the CSP techniques employ a flexible, electrically insulating substrate made from a polyimide resin material or the like and arranged on one side of which a BGA arrangement of solder bumps are disposed two-dimensionally. More specifically, a CSP type semiconductor device is provided having a semiconductor chip fixedly bonded to a flexible insulating substrate by an adhesive layer of an electrically non-conductive epoxy resin material known as Dia-touch material, connected with wirings, and encapsulated in a protective resin. Then, the BGA type semiconductor device is mounted on an external substrate (a printed circuit board) using a mounter and its solder bumps are fused by a batch reflow technique.
It is essential for mounting the semiconductor device to improve the packaging reliability. Generally speaking, the BGA package is lower in the reliability than a QFP (quad flat package) device. It is known that the CPS type semiconductor device often exhibits a crack in the joint between the external substrate and the solder bump when subjected to a thermal cycle test, resulting in open failure. It may be caused by the shear force which is produced by the effect of a difference in the linear expansion coefficient between the semiconductor chip and the external substrate and intensified at the joint. That is, as the elasticity of the flexible insulating substrate and the Dia-touch material disposed between the semiconductor chip and the external substrate is significantly lower than that of the semiconductor chip or the external substrate, the shear force will be generated by the effect of a difference in the linear expansion coefficient between the two and intensified at the joint of the soldering.
Such electronic appliances are commonly carried by users for use. Hence, the electronic appliance may be threatened by a mechanical stress such as deflection or twist due to mishandling during the transportation or the operation. This will result in injury or breakage of the integrated circuit chip, thus declining the function of the electronic appliance.
For avoiding the above drawback, the integrated circuit chip is assisted by a supporting member. In a known manner, each integrated circuit chip after separation is bonded with the supporting member which has been sized equal to the chip. The known manner will however increase the processing time, the number of manufacturing steps, and the overall cost. For compensation, some methods have been developed where the supporting member is bonded to the back side of a semiconductor substrate and then the both are subjected to a dicing process at once or separately (as disclosed in Japanese Patent Laid-open Publications No. 2000-124162 and No. (Heisei)11-67699).
However, even when the method disclosed in No. 2000-124162 states that its resultant integrated circuit chip assisted with the supporting member made of a metallic material is free from the generation of burrs after the dicing process using a CBN blade, the dicing starting from the primary side of the semiconductor substrate (on which the integrated circuits are arrayed) may produce burrs ranging from 10 μm to 100 μm at the lower side of the supporting member. Also, the dicing starting from the back side (the reinforcement side) may produce burrs of 10 μm to 100 μm at the upper side of the supporting member extending towards the semiconductor substrate. The method disclosed in No. (Heisei)11-67699 states that the dicing of the supporting member made of a metallic material is carried out using a dual dicer but fails to eliminate the generation of burrs ranging from 10 μm to 100 μm which appear at the lower side of the supporting member when the dicing starts from the primary side similar to that of the previous method of No. 2000-124162. Such burrs result in the handling error or the mounting error of the integrated circuit chip, hence interrupting the productivity at stableness.